Large arrays of two-terminal memory cells can require an isolation device (non-ohmic device—NOD) in order to avoid having substantial current flow through unselected or half-selected memory cells. Conventional approaches include using a metal-insulator-metal (MIM) diode as a device through which current can flow in either polarity of applied voltages during data operations (e.g., read and write operations) to a selected memory cell. However, in some configurations, the MIM diode can exhibit a sufficiently high “half-select” leakage ratio, that is, some current continues to flow through half-selected memory cells.
It is desirable to eliminate leakage currents associated with half-selected and un-selected memory cells during data operations, especially during read operations where the leakage currents can reduce the ability of sense circuitry to accurately sense a read current generated by one or more selected memory cells. Leakage currents can reduce a signal to noise ratio (S/N) resulting in read errors. Therefore, a high the S/N ratio is desirable and reducing or eliminating leakage currents can improve the S/N ratio. Furthermore, a high S/N ratio can reduce the complexity and size of the sense amp circuitry used for reading data from memory cells during read operations.
Reference is now made to FIG. 1A, where a schematic of a conventional memory array 150 includes a plurality of memory cells 100 arranged in a cross-point configuration with each cell 100 including a conventional MIM diode 106 electrically in series with a memory element 121, a first terminal 102, and a second terminal 104. The first terminal 102 is electrically coupled with a conductive array line 112 (e.g., a column line) and the second terminal 104 is electrically coupled with a conductive array line 110 (e.g., a row line). The conventional MIM diode 106 comprises a conventional non-ohmic isolation device. The array 150 depicts three row conductive array lines denoted as row-1, row-2, and row-3, and three column conductive array lines denoted as col-1, col-2, and col-3. The array 150 can include fewer or more conductive array lines and memory cells 100 than depicted in FIGS. 1A and 1B.
In FIG. 1A, voltage potentials for a data operation (e.g., a read or write operation) are applied to the row-2 and col-2 conductive array lines (depicted in heavy line) to select a specific memory cell 100′ in the array 150 for the data operation. Here the data operation is a write operation to program the selected memory cell 100′ (e.g., a programming operation). A voltage potential +V1 is applied to conductive array line row-2 and a voltage potential −V1 is applied to conductive array line col-2 such that the potential difference across the selected memory cell 100′ is: +V1−(−V1)=+2V1. A potential of 0V is applied to all remaining conductive array lines. Accordingly, a table 170 depicts the potential difference across the memory cells 100 in the array 150. Memory cells 100 having only one of their two terminals (102 or 104) electrically coupled with the row-2 or col-2 conductive array lines are half-selected memory cells 100 because they have one terminal at 0V and other terminal at +V1 or −V1. Therefore, the potential difference across those memory cells 100 is +V1 (e.g., +V1−0V or 0V−(−V1)). Similarly, memory cells 100 having both terminals (102 and 104) electrically coupled with conductive array lines at the 0V potential are un-selected memory cells 100 with a potential difference across those memory cells 100 being approximately 0V.
Turning now to FIG. 1B, the array 150 is schematically depicted during an erase operation to the same selected memory cell 100′. Here, the polarity of the applied voltages on conductive array lines row-2 and col-2 is the opposite of that depicted in FIG. 1A such that the voltage applied to row-2 is −V1 and the voltage applied to col-2 is +V1 resulting in a potential difference across the selected memory cell 100′ of: −V1−(+V1)=−2V1. A table 190 depicts the potential difference across all the memory cells 100 in the array 150 with un-selected memory cells 100 having a potential difference of approximately 0V and half-selected memory cells 100 having a potential difference of −V1.
Moving now to FIG. 2, an I-V curve for the memory cells 100 with the conventional MIM diode non-ohmic isolation device 106 depicts current flow I (on the y-axis) through a memory cell 100 as a function of the voltage V (on the x-axis) applied across the memory cell 100. For program and erase operations on the memory cell 100 (e.g., selected memory cell 100′), the magnitude of the current I is highest at operating point 212 for the applied voltage of +2V1 and operating point 214 for the applied voltage −2V1. The magnitude of current I is expected at those levels of applied voltage for a selected memory cell 100′ because that cell is being programmed or erased. However, for half-selected and un-selected memory cells, some current I still flows as depicted at operating points 215 and 217 for applied voltages of +V1 and −V1, respectively. Although operating points 215 and 217 are depicted at +V1 and −V1, moving along the voltage axis from −V1 to 0V or +V1 to 0V, some current I still flows through memory cells 100. For example, if the applied voltage across un-selected memory cells 100 is not exactly 0V, then a voltage potential exists across those memory cells 100 and some leakage current can flow through those cells.
Although the FIGS. 1A through 2 depict applied voltages for program and erase operations, for read operations where the magnitude of the voltage applied across the selected memory cell 100′ is typically less than that applied for program and erase operations, there will still be un-selected and half-selected memory cells in the array 150 having a potential difference across their terminals (102, 104) that can generate leakage currents that lower the aforementioned S/N ratio during read operations. Ideally, a non-ohmic device would allow current to flow only through selected memory cells 100′ and would block current flow through half-selected and un-selected memory cells 100. Preferably, the operating points for half-selected and un-selected memory cells 100 would be on the voltage axis V where the current I is 0 A.
There are continuing efforts to improve selection devices for non-volatile memory.
Although the previous drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the FIGS. are not necessarily to scale.